Integrated circuit devices, such as integrated circuit memory devices, and more specifically flash memory devices, include large numbers of active devices such as transistors. For proper operation, the transistors are generally electrically isolated from one another. As the integration density increases, and device dimensions decrease, device isolation has become increasingly difficult.
Various technologies have been developed for improving device isolation. For example, local oxidation of silicon (LOCOS), poly buffered LOCOS and trench isolation have been widely used. In the above technologies, a channel stop impurity layer is often formed beneath a field insulating layer, to improve isolation. The structure of the channel stop impurity layer can impact the effectiveness of device isolation.
FIG. 1 is a plan view showing a portion of a memory cell array area of a conventional NAND type flash EEPROM memory device. The structure of the memory cell array area shown in FIG. 1 will now be described. Reference numeral 20 represents a memory cell array area. The memory cell array area 20 is divided into an active area 1 and a field area 3. A word line 5 and select transistor lines 7 and 9 are arranged as shown, intersecting the field area 3. Contact holes 13 for connecting the active areas 1 to a metal wire (not shown) are arranged in the active areas 1 between the two adjacent select transistor lines 9. The area in which the word lines 5 are arranged, and the area in which the select transistor lines 7 and 9 are arranged, are referred to as a "memory cell area" CA and a "select transistor area" SA, respectively.
Memory cell transistors 19 are arranged between the select transistor lines 7 and 9 and pass through the active areas 1. In order to electrically isolate the memory cell transistors 19, channel stop impurity layers 37, 38 and 39 are arranged in the field area 3.
FIG. 2 is a cross-sectional view showing a portion of the memory cell array area 20 of FIG. 1, along line A-A' of FIG. 1. A first field oxide layer 35 is formed in the field area FA of the memory cell array CA of a semiconductor substrate 21. A second field oxide layer 36 is formed in the field area FA of the select transistor area SA. A first channel stop impurity layer 37 beneath the first field oxide layer 35, extends laterally across the entire field area FA to the active area AA. A second channel stop impurity layer 39 beneath the first field oxide layer 35, is formed only within the field area FA. Also, a third channel stop impurity layer 38, extending laterally across the entire field area FA to the active area AA, is formed beneath the second field oxide layer 36.
FIGS. 3 to 7 are cross-sectional views illustrating a method for fabricating the memory cell array area 20 of FIG. 2. FIG. 3 shows fabrication of a pad oxide layer 23, a polysilicon layer 25 and a nitride layer 27 on a semiconductor substrate 21. The nitride layer 27 formed on the polysilicon layer 25 is an oxidation prevention layer, to prevent the oxidation of the polysilicon layer 25 and the semiconductor substrate 21 when a field oxide layer is later formed by a thermal oxidation process. The pad oxide layer 23 is used as a buffering layer to alleviate stress between the nitride layer 27 and the semiconductor substrate 21.
FIG. 4 illustrates the step of defining an active area AA and a field area FA. In detail, a photoresist layer is formed on the nitride layer 27 and then patterned to form a photoresist pattern 29A defining the field area FA. The nitride layer 27 is etched using the photoresist pattern 29A as a mask. The portions of the nitride layer 27 which are etched define the field area FA and the portions of the nitride layer 27 which are not etched define the active area AA. Then, the photoresist pattern 29A is removed.
FIG. 5 is a diagram illustrating the step of implanting first channel stop impurity ions into the field area FA to form a first channel stop impurity layer. In detail, first channel stop impurity ions 26 are implanted into the entire upper face of the semiconductor substrate 21. The impurity implantation energy is based on the thickness of the multi-layered structure of the nitride layer pattern 27A, the polysilicon layer 25 and the pad oxide layer 23, so as to prevent the implantation of the first channel stop impurity ions 26 into the active area AA.
FIG. 6 illustrates implanting second channel stop impurity ions 28 to form a second channel stop impurity layer 39 in the field area FA of the memory cell area CA. In detail, a photoresist layer is formed on the entire upper face of the multilayered structure described in FIG. 5, and then patterned to form a photoresist pattern 33A, having a hole 15A which is more narrow than the field area FA of the memory cell area CA.
Then, the polysilicon layer 25 is etched using the photoresist pattern 33A as a mask. The second channel stop impurity ions 28 are then implanted into the entire face of the semiconductor substrate 21. Implantation energy of the second channel stop impurity ions 28 should be controlled to implant the second channel stop impurity ions 28 within the first channel stop impurity layer. Also, the concentration of the second channel stop impurity ions 28 should be higher than that of the first channel stop impurity ion 26 shown in FIG. 5. The implantation energy of the second channel stop impurity ions 28 should be based upon the thickness of the multilayered structure formed of the photoresist pattern 33A, the nitride layer pattern 27A, the polysilicon layer 25 and the pad oxide layer 23, to prevent the implantation of the second channel stop impurity ions 28 into the active region.
FIG. 7 is a diagram illustrating the step of forming the field oxide layers and the first and second channel stop impurity layers. After removing the photoresist pattern 33A, the remaining structure undergoes a thermal treatment. Accordingly, the pad oxide layer 23 is grown as the first and second field oxide layers 35 and 36 while the polysilicon layer 25 of the field area FA is oxidized. Also, the channel stop impurity layers formed in the field area FA are diffused during the thermal process.
As a result, the first and second field oxide layers 35 and 36 are formed in the field areas FA of the memory cell area CA and the select transistor area SA, respectively. Also, the first channel stop impurity layer 37 and the second channel stop impurity layer 39 are formed beneath the first field oxide layer 35, wherein the second field stop impurity layer 39 is included in the first channel stop impurity layer 37. At the same time, the third channel stop impurity layer 38 is formed beneath the second field oxide layer 36.
The first channel stop impurity layer 37 is diffused laterally over the field area FA and into the active area AA, however, the second channel stop impurity layer 39 is formed to be more narrow than the field area FA. The third channel stop impurity layer 38 is diffused laterally over the field area FA and into the active area AA, like the first channel stop impurity layer 37. Subsequently, the nitride layer pattern 27A, the polysilicon layer 25 and the pad oxide layer 23 are etched.
As described above, according to a conventional method, the channel stop impurity layers 37 and 38 formed in the memory cell area CA, extend into the active area AA, thereby reducing the channel width of the memory cell transistor which is formed in the active area. As a result, the drive current or junction breakdown voltage of the memory cell transistor may be reduced. Also, when reading information from the memory cell transistor, hot electrons may be generated at the interface between the channel of the transistor and the channel stop impurity layer to form a trap in the gate oxide layer, thereby reducing reliability. Finally, it is difficult to use photolithography to form the transistors of the flash memory cell when the highly integrated flash memory device has a submicron spacing between the transistors.